In a computer system it is common to have several modules which must compete for system resources. For example, a computer system may have several input output (I/O) devices each of which need to be serviced at various times by a processor. Sometimes more than one such module may require servicing at the same time. To operate efficiently when several modules are contending for access to a resource, the computer system must have some method for determining which of the modules to service first. The process of selecting one module from a set of modules which are competing to access a certain resource or to perform a certain operation is called "priority arbitration".
Distributed arbitration mechanisms employ an arbitration bus, comprising of a number of bus lines. Each module is connected to the bus and is assigned a unique arbitration priority. The arbitration priority of each module is represented by a unique priority code which, in general, can serve as an address for the module. The process of priority arbitration identifies the contending module with the highest priority so that that module can be given first access to the resource.
During arbitration, each module applies logic values which identify the module to the arbitration bus. The logic values applied by a particular module are determined by the priority code of the module and the logical state of the bus. After a delay, the logic values on the bus uniquely identify the contending module with the highest priority. This delay is determined by several factors including the delay through the logic components of arbitration logic as well as the time needed by the bus line to settle to a stable (binary) state.
Two major types of distributed priority arbitration mechanisms are: synchronous arbitration, which uses clocked arbitration logic; and asynchronous arbitration, in which the arbitration process is carried out by propagating signals through various stages of logic components and wires without using a global clock. Asynchronous arbitration schemes must ensure that the arbitration process is purely combinational with no feedback. In asynchronous arbitration schemes the arbitration bus and the arbitration logic of the modules connected to it must form an acyclic circuit. Feedback paths may introduce metastability and indefinite postponement of arbitration.
Taub, Contention-resolving Circuits for computer Interrupt Systems Proceedings of the IEEE, Vol 23., No. 9, September, 1976, pp. 845-850 describes a distributed priority arbitration technique. Taub's mechanism is asynchronous and requires a bus of width K=log.sub.2 N bits to arbitrate among N modules in K units of bus-settling time. This arbitration scheme has gained popularity and is used in many modern bus systems, such as Futurebus+, M3-bus, S100 bus, Multibus-II, Fastbus, and Nubus.
Kipnis, U.S. Pat. No. 5,101,482 describes an asynchronous priority arbitration system. The Kipnis system provides a trade-off between bus width (i.e. the number of bus lines in the bus) and arbitration time (i.e. the number of iterations needed to resolve contention). This trade-off is achieved by selecting the priority codes from a special group of code words which Kipnis calls "binomial codes". The number of 1-bits in a binomial code is not fixed and is often comparable to the length of the binomial code.
When the binomial codes have a length in bits equal to the number, K, of bus lines and the maximum number of intervals of consecutive 0-bits or consecutive 1-bits in the binomial codes (disregarding leading 0-bits) is t then the arbitration can be completed in t units of bus settling time. With the Kipnis system the number N of modules that may be connected to an arbitration bus is given by: ##EQU1##
Other general discussions of asynchronous and synchronous arbitration schemes can be found in Kipnis, Priority Arbitration with Buses, Proceedings if the MIT Conference on Advanced Research in VLSI, Cambridge Mass., 1990, pp 154-173 and Andrews, Enhancing the Performance of Standard Buses, Computer Design, September, 1991.
In prior art arbitration systems, the number of elementary components in a module's arbitration logic is proportional to the bus-width K. Furthermore, in many prior art systems, each module is connected to all bus lines (i.e. the number of bus lines connected to each module is K, and the number of modules per bus line is N). This reduces the performance of prior art arbitration systems because, in general, a bus line which is connected to many modules takes longer to settle to a steady state after it has been written to than a bus line which is connected to fewer modules. Other limitations of many prior art priority arbitration systems are: the design of the arbitration hardware depends upon bus width and, in some cases, the number of modules connected to the bus; and the fan-in of certain logic gates in the systems can be as large as the bus width. This is undesirable because logic gates with a large fan-in tend to be slower than equivalent logic gates with a smaller fan-in. While prior art systems can be designed with multi-level logic circuits to reduce fan-in to acceptable levels the propagation delay through such multi-level circuits is still a function of bus width.